Programmed batch sequence controller



Sept 27, 1966 E. w. YETTER PROGRMMED BATCH SEQUENCE CONTROLLER 9Sheets-Sheet l Filed Aug. 2l, 1961 mUZmDGmw lmOddOFw EOON .F3n Z-24.1005

@NH J INVENTOR. EDWAR D W.YETTER BY WW? 37m ATTORNEY Sept. 27, 1966 E.w. YETTER 3,275,983

PROGRAMMED BATCH SEQUENCE CONTROLLER Filed Aug 2l. 1961 9 Sheets-Sheetf1 DEVICE NUMBER FROM HHG INSTRUcTlI PROGRAM DCCOD'NG STORAGE MATQIXORDER IIb oN-OFF SELECTION GATES FLIP-nop SwITcI-IING LOGIC SYSTEM FIELDOR F INSTRUMENT INPUTS I" 26d FIGB CENTRAL ANDGATE ADVANCE SIGNAL HCI/OEVICE NUMBER @ggg/AM INSTRUCTION STORAGE OECOOING ,J Hb MATRIX ORDERFLIP-nop POWER AMPLIFIER [1G13 INI/EATON.

ON OFI- EDwARO wxETTER TO FIELD By a( ACTUATED DEVICES (bug ATTORNFYs@Pt- 27, 1955 Ev W. YETTER PHOGRAMMED BATCH FLW" QUENCE CONT @LIJN 9Sheets-Sheet Filed Aug. 21. 196].

Sept 27, 1966 E, w. YETTER PROGRAMMED BATCH SEQUENCE CONTROLLER 9Sheets-Sheet Filed Aug. 2l. 1961 Y JPZwDOmm| 202 11T 1w. D Q10 R A Tw w.mOE

ATTORNEY Sept 27, 1966 EA w YETTER 3,275,988

PROGRAMMED BATCH SEQUENCE CONTROLLER EOWAR D W. Y E TTER ATTORNEY Sept-27, 1966 E w. YETTER PRGRMMED BATCH SEQUENCE CONTROLLER 9 Sheets-Sheet 6Filed Aug. 21, 1961 Kwam@ A mmDZ MUSE EDWARD W'YETTER BY JN/M?? WCM?ATTORNEY Sept. 27, 1966 E. w. YETTER 3,275,988

PROGRAMMED BATCH SEQUENCE CONTROLLER Filed Aug. 21, 1961 9 Sheets-Sheet'7 CIMAL l m m 2' .n zo 1` 00 m 9 I E l I a? O o o o I DEVICE g2 g 8 E oE g E o O Q 2 g NUMBER 23 o o o o Q 5 o o 9 9. 9 z l 24 o o o o Q O O Oo o o O o o ORDH J! oFF ou 9 CONDTIONAL LOGIC INVENTOR. F|G 7A EDWARD w.YETTER BY ww? www? ATTORNEY SCP- 27, 1966 E. w. YETTER PROGRMMED BATCHSEQUENCE CONTROLLER 9 Sheets-Sheet rj Filed Aug. 21, 1961 @N MN PROCRAMMeo PROGRAM STO RA (a E AND P H. L E W. il m T O ooo: UL/ C o. N N 0:9Mm mm, 2 m 2 mm o o. oo o Ts oo P 0.09 l co9 z s 0009 m L 8 2 o m f F IT O x/O H l L A E A T. S mm S/ us k Ww o IIL C O :o .IIIIIL IlIIIIIIIIIIIIIIIIIILI INVENTOR.

EDWARD W. YETTER /WWSGMLV ATTORNEY Sept. 27, 1966 E, W. YETTER 3,275,988

PROGRAMMED BATCH SEQUENCE CONTRLLER ATTO RNEY United States Patent Oce3,275,988 Patented Sept. 27, 1966 3,275,988 PROGRAMMED BATCH SEQUENCECONTROLLER Edward W. Yetter, West Chester, Pa., assigner to E. I. du

Pont de Nemours and Company, Wilmington, Del., a

corporation of Delaware Filed Aug. 2l, 1961, Ser. No. 132,656 9 Claims.(Cl. S40-172.5)

This invention relates to improvements in batch sequence controllers,and particularly to a programmed batch sequence controller of highversatility enabling it to be applied to the control of a wide varietyof relatively complex chemical processes.

A great number of chemical processes, particularly those having as theobjective the manufacture of a relatively highcost product in a varietyofdilerent grades, such as, for example, the manufacture of dye stuffs,are of the batch type and have been hitherto operated largely undermanual control. A somewhat related controller provided with a wired-inprogram facility is taught in my copendingV U.S. application Ser. No.132,661, tiled the samedate herewith.

It is an obiect of this invention to provide a programmed batch sqeuenceautomatic controller which has suflcient capacity to encompass theprescription of all of the numerous formulations in all of the severalrespective grades included within a broad repertory of productmanufacture. It is a further object of this invention to provide a batchsequence controller which alords extreme flexibility in the choice ofsequence of process steps. Other objects of this invention are theprovision of a batch sequence controller which is low in first cost andmaintenance, has a very high reliability in operation and is adapted toextremely Wide application within the chemical arts. The manner in whichthese and other objects of this invention are attained will becomeapparent from the detailed description and the drawings, in which:

FIG. l is a block diagram of a preferred embodiment of the completeapparatus according to this invention.

showing thc direction of information transmission by arrow head,

FIG. 2 is a circuit diagram of a typical unit of thc conditional logicsection of FIG. l,

FIG. 3 is a circuit diagram of a typical unit of the command logicsection of FIG. l,

FIGS. 4A and 4B, the latter of which is a continuation of the formeralong the broken line drawn across each, is a circuit diagram of apreferred design of process step sequence control section showing alostypical over-ride auxiliaries for manual," "conditiona andnon-sequential programmed control as circumstances require,

FIG. 5 is detailed information handling diagram for a preferredembodiment of program storage apparatus, together with its associatedinstruction decoding auxiliary,

FIG. 6 is a circuit diagram detailing a single unit of the instructiondecoding matrix `of FIG. 5 for a specific switching logic position,

FIGS. 7A and 7B, the latter of which is a continuation of the formeralong the broken line drawn across each,

is an over-all partially schematic circuit representation of theapparatus of FIG. l as applied to the control of a specific chemicalprocess, and

FlG. 8 is a circuit diagram of a modified subcircut arrangement whichpermits simplitied programming of process instructions.

Generally, the batch sequence controller of this invention comprises, incombination, program storage means, a conditional logic section, acommand logic section and a process step sequence control section allobtaining instructions in coded form from the program storage means asto individual apparatus to be placed in circuit effectuating apreselected control objective, means in the conditional logic sectioninitiating progression of the process step sequence control section to apredetermined process control step in later time sequence upon thesignalled effectuation of a current process control imposition pursuantto the immediately preceding process control step, and process stepprogram address selection means responsive to the process step sequencecontrol section actuating the program storage means to supplyinstructions in coded form unique to the predetermined process controlstep for repetition of the control cycle.

In somewhat greater detail, the batch sequence coutroller of thisinvention comprises, in combination, program storage means provided withinstruction decoding means, a plurality of first and second switchinglogic systems responsive to the instruction decoding means, said firstswitchig logic systems being each reserved to the monitoring of aprocess condition sensor employed in the process under control and saidsecond switching logic systems being each reserved to a switchingoperation intemal of the controller adapted Vto elfect controloperations in preselected sequence, individual gating means actuated byindividual ones or" said first and second switch ing logic systems,sub-assemblies of said rst and second switching logic systems with saidindividual gating means constituting, respectively, a conditional logicsection and a process step sequence control section, a plurality ofthird switching logic systems responsive to the instruction dccodingmeans and each reserved to the operation of a specific device which itis desired to aetuatc in accordance with an ON-OFF order, meansconnecting exclusive ones of said third switching logic systems inoperational relationship with each said specific device, subassembllcsof said third switching logic systems together with the means connectingsaid third switching logic systems to each said specic deviceconstituting a command logic section, each said section obtaininginstructions from the instruction decoding means at to identity ofapparatus to be switched into control circuit together with such controlaction as is applicable to said apparatus, means in the conditionallogic section initiating progression of the process step sequencecontrol section to a predetermined process control stcp in later timesequence upon the signalled etfectuation of a' current process controlimposition pursuant to the immediately preceding process control step,and process step program address selection means responsive to theprocess step sequence control section actuating the program storagemeans to supply the programmed instructions unique to said predeterminedprocess control step for repetition of the control cycle.

The controller of this invention is adapted to control a process inaccordance with an ordered sequence of steps programmed in fixedrelationship one with another, or in a pattern of steps selected at willbe operator intervention whenever conditions, require, or, mostcommonly, in a combination of these two modes. The control consists in aplurality of process control steps, each processing its own uniqueprocess information stored within the program storage means. The controlimposed on he process by the single operation or plurality of operationsincluded within a given step may be completed within the particular stepof imposition or, in fact, may only be commenced, particularly if aconsiderable interval of time is required for process response.Accordingly, a process control step, or, more briey, a process step," asthe terms are employed in the description and in the claims, is intendedto comprehend both substantially completed process adjustments and alsothe taking of specific action looking towards the eventual effectuationof a given process adjustment, together with related detail, such as,for example, assurance that the apparatus is in a proper condition foraction immediately following. A "control cycle" is intended to comprisethe furnishing of information forany given process control step togetherwith all controller operation responsive thereto.

Referring to FIG. l, the functional relationship of the several sectionsof the apparatus is shown, together with directional connecting linesindicating the flow of information from one section to another. Thus,the program storage means l is central to the apparatus and concurrentlysupplies the applicable program guidance unique to each stepprogressively. through instruction decoding section l1, to conditionallogic section l2, command logic section 14 and process step sequencecontrol section 15. The latter section, upon reception of advancesignals from conditional logic section`12, delivers an output signal tostep program address selection section 17 which, in turn, effects thechoice of program unique to the next process control step which follows.Thus, each individual control step requires a cycle of operation of thecontroller.

Conditional logic section 12 is the apparatus component providingassurance that all of the several control operations bullied within agiven process control step have, in fact, been performed. The termlcontrol operation" is used in a very broad sense as inclusive of, butnot limited to, the setting of valves or temperature controllers atpredetermined levels, the obtainment of metered chemical ingredientadditions, as by counter-timed pumps, conveyors or the like, or theverification that certain critical valves, such as dump valves, forexample, are closed after vessel wash-out and prior to ingredientaddition upon commencement of manufacture. The information upon thebasis of which conditional logic section I2 functions is obtained as twogeneral types of signals received from the process, which can beconveniently denote: (l) field inputs, Fl-Fn. such as obtained fromelectrical limit switches monitoring the degree or fact of the openingof valves or level control devices, for example, and (2) instrumentinputs, I|I, which include those derived from transducers responsive toany of a great variety of process progress sensing devices, such aspressure or temperature gages, viscosity measuring instruments and thelike. Obviously, the distinction drawn between F and I inputs is anarbitrary one adopted only for convenience in description, and is of noconsequence to the operation, since both constitute inputs which aretreated identically by conditional logic section 12. Similarly, controlis shown as imposed on the process via two distinct outputs from commandlogic section 14, i.c., Dl-Du, leading to field actuated devices, suchas valves, pumps, and the like, and Sl-Sm leading to auxiliary devices,such as timer or the like exercising a duration of operation control onagencies effecting process control directly.

The binary number system is employed throughout the apparatus of thisinvention and the several circuits hcrcinafter described in detail arcshown diagrammatically in the accepted logic circuit convention,omitting associated power circuitry and the like for simplicity in theshowing.

Referring to FIG. 2, there is shown the essential conditional logiccircuitry for a single control operation, togetber with the partiallyschematic connection with instruction decoding section ll. The latter isshown as a matrix, although it can just as well be a multiple-levellogic tree or other well-known type of decoding device. The matrix ofdecoder 11 consists of two sub-matrices, thc first, 11a, being reservedexclusively to identification of the individual system point within theapparatus under control whereas the second, 1lb. is reserved [or theordered condition (abbreviated order in FIG. 2) of the device at theindividual system point corresponding to lla. The information derivedfrom sub-matrices 11a and 1lb is combined to form an intelligence signalby the use of conventional on-off selection gates 18 and 19 connected asinputs to opposite sides of the bistable switching device 20. The on"state of 20, and of all switching devices (flip-flops) hereinafterdescribed, is denoted by thc numeral "1" and the o'" state by "0."

The purpose of the conditional logic section is verification thatcertain ordered action has occurred, and this is obtained by the use ofan AND" gate 23, receiving as one input an IF,l or I., signal from theprocess under control via line 24, and as the other input the on" signalfrom flip-dop 20. The output of gate 23 is furnished as one input to an0R gate 25, the other input of which is the,off" signal of flip-Hop 20.Thus, with the switching logic circuit described, when hip-flop 20 is inits on" state and there has been compliance with the ordered action onthe part of the process apparatus as vcricd by the Fn or 1 responsereceived through line 24, a signal is delivered through line 26indicative of this fact. On the other hand, if the deliberate controlplan requires no ac` tion applicable to the process, tlip-op 20 isenergized to its oif," or zero, state and again a signal indicative ofthis fact is delivered through line 26. The response of all controloperations included within a single control step are combined byindividual inputs through lines 26, 26u, 26h, 26e, 26d, etc. to acentral AND" gate 27, the output of which is the "advance" signaldelivered via line 28 to process step sequence control section l5 (FIG.l).

Turning now to the detailed construction of command logic section 14shown in FIG. 3, this is very much like the conditional logic sectionalready described, in that it receives device identification from thesame sub-matrix lla and order information from the same sub-matrix 11b.This intelligence is combined in a conventional ori-oil selcction gatepair indicated generally at 3l, the two outputs of which go to oppositesides of a flip-[lop 32. In the on" state (i.c., the l side of 32), anoperative signal is delivered via line 33 to the particularheld-actuated device involved, which may be a valve drive motor or anyof a wide variety of similar control devices directly effecting thecontrol operation, and ordinarily it is desirable to amplify the signalby use of an amplifier 34. In rather unusual instances it may bedesirable to obtain -a voltage signal corresponding to the off state ofHip-flop 32 and this can be amplified, if desired, by passage through anamplifier 35 (shown in broken line convention) connected to this side ofthe tlip-llop.

The detailed logic circuitry of a preferred embodiment of process stepsequence control section 15 is shown in FIGS. 4A and 4B, and utilizesthe same sub-matrices lia and 1lb of decoding section 11 hereinbeforedescribed for the communication of the essential guidance information.This particular design of process step sequence control section permitsan cxeremely flexible and varied control imposition, as will be clearfrom the following description.

It is preferred to tie in the control rigorously to the program storage10, instead of relying solely on an advance signal received fromconditional logic section 12 as the only index for embarking on the nextprocess control step. This is accomplished by the use of AND" gate 38(FIG. 4B) receiving as one input the advance signal from line 23 and, asthe other, a signal from the on side of a program interlock flip-flop 39responsive to decoder ll for its switching to this position. Filp-llop39 is set to its on state by the final instruction in thc program forany given step, and remains on except during the relatively brief timerequired for opening the gates of program storage for reprogramming thenext step plus the reprogramming interval itself (typically a total timeof approximately 2-3 millisecs.), which is effected by a program signal"passed to 10 via line 40. Flip-tlop 39 is switched to its "off" state bya signal derived from gate 38, passed through "OR gate 41 and thence viatime delay 42 and line 43 to the oft side. Time delay 42 is provided topermit the process step storage register 46 hereinafter described toreach its setting identifying the control step to follow (typically 2 or3 microsecs.) before program interlock flip-flop 39 is energized to itszero state permitting read-out from program storage l0.

The agency accounting for individual step identification is the processstep storage register indicated generally at 46, which'consists of anarray of tlip-ops (typically 6 in number for ya control incorporating 64steps) arranged as a binary counter, the successive stages of which areindicated by the numerals 2 with exponents sucessively increasing drawnin adjacent each. Each of the counter stages is provided with anindividual step select hip-flop 46a, 46h, ctc., provided with on-offselection gates 45a, 4511, etc., similar to gates 18 and 19 hereinbeforedescribed for conditional logic section I2 and connected responsive tosub-matrices 11a and 1lb in identical manner as de- -scribed for sectionl2. These st'ep select tlip-ops store any process control step numberidentification programmed in l0 and, thereafter, in combination, insertthe specific identification into register 46 upon the added commandderived from any one of the hereinafter described circuit auxiliaries,which permits over-ride of the sequential stepby-step advance occurringunder the sole control of conditional logic section 12. Thus,collectively, step select flip-flops 46a, 46b, etc., constitute thenon-sequential step storage register for the apparatus.

Accordingly, if an emergency is envisoned requiring a spccialcourse ofaction to take place upon manual command, the process step correspondingthereto is programmed in program storage 10, given an identificationnumber within the range of register 46 and called out via manualflip-flop 47 (FIG. 4A) which is reset in the same manner as interlockflip-flop 39 by connection to time delay 42 through line 43. The manualintervention applicable to this operation is applied by pushbuttonsignal through line 48 to TAND gate 49 connected also with the output ofthe on" side of tlip-op 47 delivered through line S0. The output of 49passes to OR" gate 53, which also handles other over-ride signalshereinafter described, and thence goes via line 57 to AND gate 54wherein it is correlated withv program interlock flip-flop 39 in thesame manner as already described for a sequential signal. The output ofgate 54 is co-ordinated with individual sides of step-select flip-flops46a, 46h, etc., by connection via line 55 to AND" gates 56 reserved toeach pair of such outputs, the outputs of gate S6, in turn, beingconnected directly to the respective stages of the binary countersmaking up process step storage register 46. The operative loop circuitto the olT side of program interlock flip-flop 39 is'completed bycircuit connection from line 55 running to OR gate 4l, and thence totime delay 42 and line 43.

It may be' that it is necessary or convenient to go to a step which isnon-sequential in the programming, and this is readily accomplished byprogramming the command to take such action and calling it out through"programmed" tiip-flop 60 (FIG. 4A) which is connected responsive tomatrices 11a and 1lb also to' program interlock dip-flop 39 via line 57in the same manner as described for manual flip-flop 47, and the outputof which is delivered through line 6l to OR gate 53, after which thecommand is handled over the same circuitry and in identical manner withthat already described fof manual intervention.

Similarly, it may be desirable to go to the next step in programmedsequence even though no advance" signal has been transmitted fromconditional logic section l2 through line 28. This is readilyaccomplished by providing next step flip-flop 63 responsive to matrices11a and 11b as hcreinbefore described for flip-flops 47 and 60 andoperating similarly to 39, with output delivered via line 64 to OR" gate65, thereafter employing the identical circuitry already described forsequential step indexing to advance register 46 one number.

Finally, it might be desirable to carry out a given procedure, such asemergency vessel evacuation, for example, when one or more sensedconditions are found to exist, and this is accomplished through theconditional" sub-circuit shown in the left-hand side of FIG. 4A. Theexample detailed involves the situation where, if two specific lieldinputs denoted Fo and Fm, respectively, exist simultaneously when thevpreceding logic circuitry is in its on" state, the emergency action willbe taken. On-otl? selection gates 68 and 69 responsive to matrices 11aand 1lb and connected to opposite sides of ip-llops 70 and 71,respectively, in the same manner as hereinbefore described for theconditional logic circuit of FIG. 2 are employed as the logic circuitry,thereby providing the actuation of section l5 4by use of AND" gates 72and 73. The coincidence of the emergency conditions is sensed by ANDgate 74 delivering its output signal via line 75 to OR 53, from whenceit is processed in identical manner with the manual and other over-rideshereinbefore described.

Referring to FIG. 5, the program storage and address selectioncomponents of the apparatus are of conventional design and operation,all as described in Logical Design of Digital Computers" by MontgomeryPhister, J r., chapter 7, .lohn Wiley & Sons, N.Y., publishers (1958),and are therefore herein described only functionally.

The magnetic storage drum 79 is provided with a multiplicity ofcircumferential tracks made up of magnetized spots, which are read outby magnetic heads (not shown), the three left-hand ones of which areclock tracks in thc usual time graduation of one information bit for thefirst in order from the left, one word for the second and one block forthe third, although the single bit track is basic and the onlyindispensible one, since pulse counters can be substituted for each ofthe others if circumstances rcquire. It will be understood that thethree clock tracks serve as the gate synchronizing controls, eachcontrolling entirely independent of the others but spaced around thecircumference of the drum so that the word track spots are spaced aparta distance such that they occur at the first bit of a convenient wordunit adapted to the informational transfer neccssary to achieve theover-all control sought, whereas the block track spots are spaced to licon the first bit of the first word of a convenient size of total ofinformation suited to handling as an entity. Thus, in terms ofinformation flow, a word unit can consist of an address and orderinstruction, whereas a block unit can consist of a convenient groupingof a fixed or average number of words necessary for a fraction or anentire process step. The remaining tracks (not shown) are the codedprogram information tracks, of which there may typically be in totalnumber, each program being entered in circumferential sequence on asingle track and any excess carried over to the next adjacent track.Each bit of information is read out serially and the composite wordaccumulated as a multidigit number in shift register 8l, after which theentire word is read out by multiple gate 82, the outputs from which godirect to device identication sub-matrix 11a and order sub-matrix 11b ofintsruction decoding section 1l. The details of circuitry of register 81and its associated components are shown more fully in FIG. 6.

The internal control of program read-out is obtained in two ways: (l) asa space selection information derived from process step storage register46 as denoted by lines 83, FIG. 5, running to step program addressselection section 17 and (2) as a time co-ordination based on threeseparate co-existing sensed conditions, namely, time track read out fromdrum 79, reception of the program signa-1" hercinbefore described vialine 40 and a program step identification derived via line 84 fromregister 46. The section of 17 accomplishing the last-mentioned time coordination also correlates the operation of gate 82 through line 8S.

It is preferred to incorporate as an auxiliary a conventional partycheck applicable to information as it is con- 4tinuouslyread out fromsection 17. This can consist of asingle stage flip-flop 86 connected vialine 87 so as to be actuated by information pulsestransmitted to shiftregister 81. lf one bit space is 4reserved as an` addition to makeadwords contain an odd number of ones, it is apparent that anyeven-numberedsignal sequences received by 86 will4 represent an error.Analarm 71 indicative of this fact then provides the `operator withnotice that an error has occurred, and timelyremedial action can then betaken.

As shown in FIG. 6, the device' identification section of 'shiftregister 8l consists of a plurality'of bistable switching devicesarranged to reeeivelsuceessively the ac tuatingl or information 4pulsessupplied via line 88 in sequence from section 1'7 and storevtheresulting indication until the accumulation is gated out simultaneouslyby mul tiple gate 82. Each ot' ,the bistable devices of `81 is, ineffect, a' flip-Hop, the ranges ofwhich Yare denoted by the appropriatepowers of two. The device order" section of* register 81 consists ofindividual bistable switches 89 and 90, reserved, respectively, for onand olF actuation of the specific devices identified by theidentification section of 81, which receive their inputs from section 17via lines 91 and 92, respectively.

The AND' gating connection for a single position, namely thatcorresponding to the number 11101, is shown in FIG. 6 as control for theon-olf gate pair indicated generally at 93, corresponding to any of thegate pairs 1849,

31 or the equivalent hereinbefore described. A meaningful signal interms of an 0n" or oif1 operation of n specific device is obtained ashereinbefore described by ANDING the outputs of bistable switches 89 and90 with the device designation signal received via line 9S to theappropriate side of the responsive ip-op 96, which latter corresponds to20 and the other iptlops with similar function already described.

Referring to FIGS. 7A and 7B, the operation of the apparatusof thisinvention is described with particular reference to chemicalmanufacturing equipment utilizing a variety of components which eachnecessitate control and verification operations. Thus, there is a4pressure reaction vessel 100, which is provided with a compressor 101conn nccted therewith via motorized valve V1 (energized to cipen) andthe vessel is further provided. with a motorized discharge'valve V,(energized to close). The valves are provided with limit switches V1,and V2., the former indicating, when closed, that V1 is open whereas thelatter indicates, when closed, that V2 is closed. P, is apressure-responsive switch set ata specific pressure level which it isrequired to attain prior-to carrying the process to later step ashereinafter described. Pz is a pressure-rt sponsive switch set to adilerent and higher pressuri l than P1, P2 sensing an emergencyconditionrequiring immediate corrective action, such as, for example, evacuationof reactor 100, when the temperature sensed by ternperaturc sensingdevice Tl, provided with limit switch contacts T15, reaches a givenvalue. Time duration control is effected by conventional binary counter103 (FIG. 7A) which is actuated by the usual time pulse source 104.

The sequence of proces operations which it is desired to perform in theorder of steps detailed, is as follows.

Step No. l:

Close outlet valve V2, Open inlet valve V1, Check to determine that thevalves are both operated as ordered in the two previous operations.

Step No. 2: Start compressor 101 and continue its operation until apredetermined pressure, i.e., the set pressure of P1, has been reachedin reaction vessel 100.

Step No. 3:

Stop compressor 101,

Close inlet valve Vl,

Allow the reaction to continue for seven time units before proceeding tothe next step. (If, during this reaction period, the pressure signalledby P, and the temperature signalled by T1 both reach unsafe valuescorresponding to the set points of their respective switch contacts,immediately proceed with a programmed shut down as provided by Step No.14).

Step No. 4: Jump to Step No. 9 (a stepdictated, for example, by a specicproduct recipe requirement).

Steps No. 5 through No. l2 (not detailed): Relate to bringing themanufacture to completion.

Step No. 13: Reset the control apparatus and prepare for a new batch.

Operation of the apparatus of this invention consists in the selectionof the identifying number of the appropriate switching logic systems(indicated generally as blocks 102 in FIGS. 7A and 7B) and selecting thedesired state for each, i.e., 0" or l, corresponding `to OFF and 0N,respeclively. The order in which instructions appear in the programstorage, or are fed to the several logic systems, is ordinarily of noimportance except in the specilc case of the Program Interlock."

Operation as hereinafter described utilizes a ivc bit device number anda two bit order, the time sequence in which the bits appear seriallywhen read from program storage 10 being: (l) live bit device number,with least signicant digit first and (2) two bit number, as to which l()signiflcs the 0" or OFF state and 0l signifies the 1" or ON state. Thus,in parallel form, as the complete instruction is accumulated in shiftregister 81 of FIG. 5, a typical instruction in binary code can be l0H001 which, translated, will be: Set device No. 25 to the OFF (or 0")condition. As an aid in understanding, both the decimal and binary codeidentifications of the several devices under control are indicated bythe columns of numbers provided along the top margins of the drawings.The main section blocks, together with parts of associated matrix 1l andtypical switching logic systems, are indicated schematically .to moreclearly tie in the operation with the apparatus hereinbefore describedin detail with refernce to FIGS. 1 6.

The initial condition of the controller at startup is as follows:

( l) The program interlock logic system 102is in the ON (or 1) state,

(2) The conditional logic switching system to which the Start pushbuttonswitch (FIG. 7B) is connected (denoted deviee No. 14 in this example) isin the 0N (or l") state, and

(3) The number stored in the process step storage register 46 (FIG. 4B)is 0000.

The program for the several steps will then be:

Instrucf Dcvloe No. tion No.

000m-Close Vl 00001- pen Vt.

0l M10-Connect Vg. limit switch.

0l l01 Connect Vl. limit switch. lutto-Set. lrogrnm interlock.(M1000-Start compressor 101. 0..011-Conncct P1 pressure switch.ltlilo-Set Program Interlock. 000m-Stop compressor 101. 000m-Close Vi.

00in-Set timer 103 2# digit to 1'. 01000--Set timer 103 2| digit to l.01001-Sct timer 103 2 digit to 1. 0mm-Disconnect v1. limit switch.mm1-Disconnect Pl pressure switch. 0h00-Disconnect V1. limit switch.0mm-Start pulse source 1M [or timer 103. M100-Connect Ti temperatureswitch. ml-Connect P; pressure switch. 10u00-Set. 2s step select, bit to1". 100th-Set 2* step select blt to 1." 10010-501. 2l step select blt to1.*l 10110-Set Program Interlock. 00110-Stop time pulse source 10i.100m-Set 21 step select hlt to 0." 100m-Set 2l step select blt to 0."10011-Set 2 step select hit to 1." 11u00-Eet Programmed hiphop 102 to 1.mno-set Program Interlock. f

[intervening Steps Nos. 5 through 12 not detailed.)

XXXXX- XXXXX- Set all devices to 03' XXXXX 011 IO-Colmect Start."10110-Set Program Interlock.

These operations collectively set timer to 7 tie., 111 ln blnnry code).

"These openlnions collectively set step select flip-flops ol register 46to 1110 lie., Step "'Theac operations collectively set stop selectfllp-tlops 40 to 1001 (1.o. stop 9).

The several infomation transmission lines in the apparatus of FIGS. 7Aand 7B are identified by the letters of the manufacturing apparatuswhich each controls as an aid in tracing operation. The operation of thecontroller in the staged sequence provided by storage drum 79 involvesthe succession of individual gating operations already described forcach of the several sections 12, 14 and 1S and, accordingly, is notrepeated here. However, several of the steps programmed are explained insupplementation of the program per se. Thus, towards the end of Step No.3, instructions Nos. 12,-14, inclusive, call for setting the flip-flopsof 46 to 1110 corresponding to Step No. 14 which, as hereinbeforedescribed in the description of manufacturing operations, is theemergency evacuation which must be conducted of P2 and T1, togethersignal dangerous process condition limits. This setting of 46 is purelyanticipatory and is necessarily maintained only during the time when thenature of the process is such that the emergency is within the realm ofpossibility. It is assumed that this time has passed as the controlsequentially proceeds to Step No. 4, which is a jump step, in that thecontrol action thereby proceeds immediately to Step No. 9 by appropriatesetting of the ilip-tiops of 46 as detailed. In this connection, it willbe understood that it is not necessary to reset the 23 flip-nop of 46,because this was already set to "l" by instruction No. 12 of Step No. 3.

It is possible to reduce the number of diodes required for instructiondecoding section 11 as regards the setting of registers generally, suchas counter 103 of FIG. 7A and the non-scquential step select register ofFIG. 4B, by utilizing .the form of matrix and auxiliaries shown in FIG.

8. Again, the sections of the register applicable to devicc designationand order command are denoted 11a and 11b, respectively, with theassociatcd"pairs of horizontal excited lines identified 1" and 0 for theseveral energizing stages of register 81 corresponding to 2s, 22, 21,and 2 drawn adjacent thereto.

The embodiment of FIG. 8 requires an individual switching logic systcmdenoted generally an 107 for each register to bc controlled, this systembeing similar to ihosc hereinbefore described with reference .to FIGS.2, 3, 4A, 4B, and 6 except that there is interposed a time delay device108 (typically 5 microsecs. duration) between the onolf selection galepair 107a and the 0N" side of the responsive flipdlop 107b. A controlline 109 routes the signal without time delay to the OFF," or 0," sidcsof all of the ip-ops l10n, 110b, 110C, and 110e! which set theindividual stages of the register controlled, only four of theseflip-hops being shown in FIG. 8 although there will ordinarily be more(e.g., eight ilip-ilops provide a capacity vof one hundred, as comparedwith a capacity of 256 for a straight binary system).

The output from the 0N side of flip-flop 107b is passed via line 112 asone input to each of the register control AND" gates p, 110g, 110r, and110s having outputs connected to the ON" sides of hip-flops l10n, 110b,110e, and 110d, respectively. The other inputs to these AND gates arederived from three-input AND gates Ua-1164, respectively, the inputlines of which go to the appropriate 1 side conductors of matrix 11a andto the 0" conductors of both the ON and "OFF sides of the order pairs of11b. Finally, the ON outputs of ip-flops .110a110b110c, and 110e! aremade available for any purpose desired via lines 117, whereas the 0 sideoutputs are shown combined as a single signal via lines 118,`constituting thc several inputs to a common gate 119, or utilizedindependently as hereinafter described. l

The advantage of the circuit of FIG. 8 is 4that it permits the settingof registers with only three instructions, as compared with the muchgreater complexity involved in single-bit register actuation. Completelyapart from this, decimal register settings are generally preferred byprogramming personnel who donot have extensive binary number systemexperience, and who therefore find it more convenient to insert theinstruction program in drum 79 using the decimal system throughout. Thisis readily accomplishcd in the conventional manner known to the art byencoding the device numberv portion of the instruction word in abinary-coded decimal form. It will be undcrstood that, to utilize thedecimal system and the apparatus of FIG. 8, it is necessary to use eightbits for device designation, two bits for order instruction and a singleparity bit as hereinbcforc described, making a total of clcven bits, ascompared with the somewhat smaller requirement of eight bits for thesystem of FIGS. 1-7A, 7B.

The operation of the embodiment of FIG. 8 is as follows. The rstinstruction receivcd from matrix 11u by switching logic system 107selects the appropriate register and immediately sets all of thetlip-i'iops l10n-110:1 lo 0 state by signal passed along line 109. Afterthe slight time delay afforded by time delay device 108, the duration ofwhich is preselected to be such that all ip-ops 110a-110d will havereached their 0" states bcl'orc gatcs 0p-110s, inclusive, are gated openby iiip-tlop 107b, tlip-op 107b is switched to its ON" position.

The sccondinstruction introduces the numerical information into theregister by setting individual ilipflops l10n-1.1M to the "ON" state, asdictated by the matrix 11a wired ,connections In order to avoidambiguity which might arise due to identically coded order instructions,AND 116a-116d are employed, which AND only responsive to a 00 conditionof matrix 11b, which is a distinctive state not, of course, achieved by1 1 either of the two states 10 and 01 relied on for order informationtransmission.

The third instruction is simply an OFF" order to switching logic system107, which order gates Hop-110s to close and restores the circuitry toits original state.

lt will be understood that, if no tied-in response is reqired, commonAND" gate 119 can be dispensed with and connections made to eachindividual "OFF" (or 0") side of llip-ops 'lltla-lllld in a circuitsimilar to that of the step select hip-flops 46a and 46h of FIG. 4B andoperating in the same manner as already described.

The controller described in detail has a tlexibility accommodating agreat variety of manufacturing processes; however, where the controlleris to be used on a single process it is entirely practica-ble to employa fixed programming device, such as, for example, one incorporatingwired magnetic cores, as a substitute for the magnetic storage drum.

It has been determined in practice that the controller of this inventionis well-suited to the concurrent control of a number of processes byutilizing conventional multiplexing techniques, making it possible touse a single program storage means and its associated instructiondecoding means for a plurality of processes to be controlled. ln suchinstallations, it is desirable to incorporate a tirst come-first serve"interlock to permit the orderly disposition of-control operations whichcall for electuation at about the same time, or means for otherwiseassuring a priority handling of one over others; however, this can bereadily done by resort to programming to take care of the eventually, orby other means of traic control known to the art.

From the foregoing, it will be understood that this invention can bemodified in numerous respects without departure from its essentialspirit, and it is therefore intended to be limited only by the scope ofthe appended claims.

What is claimed is:

tl. A batch sequence controller, comprising, in combination, programstorage means, a conditional logic section, a command logic section anda process step sequence control section all obtaining instructions incoded form from said program storage means as to individual apparatus tobe placed in circuit e'cctuating a preselected control objective, meansin said conditional logic section initiating progression of said processstep sequence control section to a predetermined process control step inlater time sequence upon the signalled elfectuation of a current processcontrol imposition pursuant to the immediately preceding process controlstep, and process step program address selection means responsive tosaid process step sequence control section actuating said programstorage means to supply said instructions in coded form unique to saidpredetermined process oontrol step -for repetition of the control cycle.

2. A batch sequence controller comprising, in combination, programstorage means provided with instruction decoding means, a conditionallogic section, a command logic section and a process step sequencecontrol section all obtaining instructions in coded form from saidinstruction decoding means as to individual apparatus to be placed incircuit electuating a preselected control objective, 4means in saidconditional logic section initiating progression of said process stepsequence control section to a predetermined process control step inlater time sequence upon the signalled electuation of a current processcontrol imposition pursuant to the immediately preceding process controlstep, and process step program address selection means responsive tosaid process step sequence control section actuating said programstorage means to supply said instructions in coded form uniqueto saidpi'cdetermined process control step for repetition of the control cycle.

3. A batch sequence controller according to claim Z wherein saidinstruction decoding means is a diode matrix.

4. A batch sequence controller according to claim 2 provided withover-ride means adapted to supersede said conditional logic section inthe initiation of said process step sequence control section topogression to the ncxtsucceeding programmed control step by substitutioninstead of a pre-selected dili'erent programmed control step.

5. A batch sequence controller comprising, in combination, programstorage means provided with instruction decoding means, a plurality offirst and second switching logic systems responsive to said instructiondecoding means, said first switching logic systems being cach rcservedto the monitoring of a process condition sensor employed in the processunder control and said second switching logic systems being eachreserved to a switching operation internal of said controller adapted toeffect control operations in preselected sequence, individual gatingmeans actuated by individual ones of said rst and second switching logicsystems, sub-assemblies of said first and second switching logic systemswith said individual gating means constituting, respectively, aconditional logic section and a process step sequence control section, aplurality of third switching logic systems responsive to saidinstruction decoding means and each reserved to the operation of aspecific device which it is desired to actuate in accordance wit-h anON-OFF order, means connecting exclusive ones of said third switchinglogic systems in operational relationship with cach said specificdcvice, sub-assemblies of said third switching logic systems togetherwith said means connecting said third switching logic systems to eachsaid specific device constituting a command logic section, each saidsection obtaining instructions from said instruction decoding means asto identity of apparatus to be switched into control circuit togetherwith such control action as is applicable to said apparatus, means insaid conditional logic section initiating progression of said processstep sequence control section to a predetermined process control step inlater time sequence upon the signalled etectuation of a current processcontrol imposition pursuant to the immediately preceding process controlstep, and process step program address selection means responsive tosaid process step sequence control section actuating said programstorage means to supply the programmed instructions unique to saidpredetermined process control step for repetition of the control cycle.

6. A batch sequence controller according to claim 5 wherein saidinstruction decoding means is a diode matrix.

7. A batch sequence controller according to claim S provided withover-ride means adapted to supersede said conditional logic section inthc initiation of said process step sequence control section toprogression to the nextsucceeding programmed control step bysubstitution instead of a pre-selected different programmed controlstep.

8. A 4batch sequence controller according to claim 5 provided with meansresponsive to instructions received from said program storage meansadapted to initiate progression of said process step sequence controlsection to said predetermined process control step in next-followingtime sequence independent of said signalled etfectuation of a currentprocess control imposition pursuant to said immediately precedingprocess control step by said means in said conditional logic section.

9. A batch sequence controller according to claim S wherein saidswitching logic system each consist of a bistable switching devicereceiving its inputs through individual AND gates connected to uniqueapparatus and device identification and order channels in saidinstruction decoding means.

(References on following page) References Cited by lhc Examiner OTHERREFERENCES `IBM Customer Engineering Manual of Inslruclion, 650

Data Processing System," Section l, Gen. Principles, 17 pp., 1956.

III

14 John Wiley & Sons, Handbook of Automation, Cornpulatinn and Control,vol..1l'1 by Ramo, Grnbbe, and Wooldridge, pp. 3-I and 3-3, i960.

ROBERT C. BAILEY, Primary Examiner.

MALCOLM MORRISON, Examiner.

W4 M. BECKER, P. J. HENON, Assistant Examim'zr.:A

1. A BATCH SEQUENCE CONTROLLER, COMPRISING, IN COMBINATION, PROGRAMSTORAGE MEANS, A CONDITIONAL LOGIC SECTION, A COMMAND LOGIC SECTION ANDA PROCESS STEP SEQUENCE CONTROL SECTION ALL OBTAINING INSTRUCTIONS INCODED FORM FROM SAID PROGRAM STORAGE MEANS AS TO INDIVIDUAL APPARATUS TOBE PLACED IN CIRCUIT EFFECTUATING A PRESELECTED CONTROL OBJECTIVE, MEANSIN SAID CONDITIONAL LOGIC SECTION INITIATING PROGRESSION OF SAID PROCESSSTEP SEQUENCE CONTROL SECTION TO A PREDETERMINED PROCESS CONTROL STEP INLATER TIME SEQUENCE UPON THE SIGNALLED EFFECTUATION OF A CURRENT PROCESSCONTROL IMPOSITION PURSUANT TO THE IMMEDIATELY PRECEDING PROCESS CONTROLSTEP, AND PROCESS STEP PROGRAM ADDRESS SELECTION MEANS RESPONSIVE TOSAID PROCESS STEP SEQUENCE CONTROL SECTION ACTUATING SAID PROGRAMSTORAGE MEANS TO SUPPLY SAID INSTRUCTIONS IN CODED FORM UNIQUE TO SAIDPREDETERMINED PROCESS CONTROL STEP FOR REPETITION OF THE CONTROL CYCLE.